Typically, the design process of an analog IC begins with the development of a schematic diagram based on a set of specifications. The set of specifications includes estimated parasitic resistance, capacitance and inductance values for the components of the schematic diagram. The schematic diagram is then simulated to verify the specifications are met. Before simulation, the estimated parasitic values (or “parasitics”) are typically increased to ensure that compliance remains during later stages of the design process. If the specifications are not met, the parasitic values can be adjusted and simulation performed again until satisfied.
After the schematic diagram is created and simulated, a layout diagram based on the schematic is created. Once the layout design has been completed, simulations are again required to verify that the layout diagram of the integrated circuit still meets the required specifications in the presence of parasitic values extracted from the layout. A full “back-annotation” of these parasitic values into the schematic of the circuit under test is required for simulation to verify performance. This can require, for example, adding anywhere between 1,000 and 1,000,000 parasitic components (depending on the size of the layout) into the schematic for simulation. The addition of these components can lead to simulations that may not converge (i.e., fail) or may have an extremely long run time. Since the range of parasitic element values can cause non-convergence or extended simulations for complex layouts, full parasitic extraction may not be feasible. Additionally, extracting the parasitic values and back-annotating these parasitic values does not intercept potential problems early in the design process. Instead, the layout is completed before the parasitic element values are extracted.
To ease extraction difficulties, some design processes may use a selected nets extraction with complex layouts. However, using selected nets extraction requires a separate extraction for each newly constrained net. Additionally, using selected nets extraction relies on the nodes in the layout that are known. As such, there is not a mechanism to specify global constraints for a circuit. Furthermore, parasitic values may be over-reported in certain situation. Accordingly, what is needed in the art is an improved method or system to ensure parasitic constraints for analog ICs are satisfied during the design process.